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 INTEGRATED CIRCUITS
DATA SHEET
TDA1548T Bitstream continuous calibration filter-DAC with headphone driver and DSP
Product specification Supersedes data of 1995 Aug 02 File under Integrated Circuits, IC01 1995 Nov 15
Philips Semiconductors
Product specification
Bitstream continuous calibration filter-DAC with headphone driver and DSP
FEATURESPRODUCT SPECIFICATION Easy application * Only first-order analog post-filtering required * Headphone amplifiers and digital filter integrated * Component saving common headphone output * Selectable system clock (SYSCLK) 64fs, 256fs or 384fs * 16, 18 or 20 bits I2S-bus or LSB justified serial input format * Input pins suitable with 5 V low supply voltage interfacing * Small package (SSOP28) * Single rail supply (3 V). High performance * Superior signal-to-noise ratio * Wide dynamic range * Continuous calibration digital-to-analog conversion combined with noise shaping technique. Features * Low power dissipation * Digital volume control * Soft mute * Digital tone control (Bass Boost and Treble) * Digital de-emphasis * Analog control of digital sound control functions. GENERAL DESCRIPTION The TDA1548T is a dual CMOS digital-to-analog converter (DAC) with up-sampling filter and noise shaper and ORDERING INFORMATION TYPE NUMBER TDA1548T TDA1548TZ PACKAGE NAME SO28 SSOP28 DESCRIPTION plastic small outline package; 28 leads; body width 7.5 mm plastic shrink small outline package; 28 leads; body width 5.3 mm
TDA1548T
integrated headphone driver featuring unique signal processing functions. The digital processing features are of high sound processing quality due to the wide dynamic range of the bitstream conversion technique. The TDA1548T supports the I2S-bus data input mode with word lengths of up to 20 bits and the LSB justified serial data input format with word lengths of 16, 18 or 20 bits. The clock system is selectable (64fs, 256fs or 384fs) by means of selection pins. Two cascaded half band filters, linear interpolator and a sample-and-hold function increase the oversampling rate from 1fs to 64fs. A second-order noise shaper converts this oversampled data into a bitstream for the 5-bit continuous calibration DACs. On board amplifiers convert the output current to a voltage signal capable of driving a headphone or line output. The common operational amplifier application eliminates the need for capacitors. The TDA1548T has some sound processing functions which are controllable by a potentiometer. These functions are volume, bass boost and treble. The flat/min/max switch can also be controlled by a potentiometer. The analog values are converted to a digital code, which is then further translated internally to a set of coefficients for either volume, bass boost or treble.
VERSION SOT136-1 SOT341-1
1995 Nov 15
2
Philips Semiconductors
Product specification
Bitstream continuous calibration filter-DAC with headphone driver and DSP
QUICK REFERENCE DATA SYMBOL VDD IDD VoFS(rms) (THD+N)/S PARAMETER supply voltage supply current full-scale output voltage total harmonic distortion plus noise as a function of signal note 1 note 2 VDD = 3 V 0 dB signal 0 dB signal; ROL = 5 k -60 dB signal; ROL = 32 or ROL = 5 k S/N BR signal-to-noise ratio input bit rate at data input A-weighted; at code 00000H fsys = 384fs fsys = 256fs fsys = 64fs fsys TCFS system clock frequency full-scale temperature coefficient at analog outputs (VOL and VOR) operating ambient temperature CONDITIONS - 0.57 - - - - - - 90 - - - 2.048 - MIN. 2.7 3.0 15 0.64 -65 0.056 -85 0.006 -35 1.778 95 48fs 64fs 64fs - 100 x 10-6 TYP. -
TDA1548T
MAX. 4.0 0.71 -60 0.1 -78 0.013 -30 3.162 - - - - 18.432 - V
UNIT mA V dB % dB % dBA % dBA
MHz
Tamb Notes
-20
-
+70
C
1. All VDD and VSS pins must be connected to the same supply or ground respectively. 2. Measured at input code 00000H and VDD = 3 V.
1995 Nov 15
3
Philips Semiconductors
Product specification
Bitstream continuous calibration filter-DAC with headphone driver and DSP
BLOCK DIAGRAM
TDA1548T
handbook, full pagewidth
IF1 13
IF2 14
DATA 9
WS 8
BCK 7 16 15 VOLUME AND SOUND CONTROL 22 21 20 19 1 fs VDDA - OP4 + 18 ADref MUTE DEEM AD3S ADVC ADBB ADTR
SERIAL DATA INPUT 12 TIMING CLSEL 17 SOUND CONTROL MODE0 MODE1 5 6 FILTER STAGE 2 4 fs LINEAR INTERPOLATOR 8 fs 8 x OVERSAMPLING (SAMPLE-AND-HOLD) 8 x OVERSAMPLING (SAMPLE-AND-HOLD) VSSA VOLUME CONTROL SOFT MUTE CONTROL
SYSCLK
FILTER STAGE 1 2 fs
2nd ORDER NOISE SHAPER DATA ENCODER
2nd ORDER NOISE SHAPER DATA ENCODER
11 10
VSSD VDDD
FILTCL
4 RCONV1 1.2 k 3 - OP1 +
16 (4-bit) CALIBRATED CURRENT SOURCES
16 (4-bit) CALIBRATED CURRENT SOURCES
26 FILTCR RCONV2 1.2 k - OP2 +
1.8 nF CEXT1
1.8 nF CEXT2 27 VOR
LEFT OUTPUT SWITCHES REFERENCE SOURCE 16 (4-bit) CALIBRATED CURRENT SINKS
RIGHT OUTPUT SWITCHES
VOL V DDA
6 k Vref 10 F V 25 6 k
16 (4-bit) CALIBRATED CURRENT SINKS
- OP3
+
TDA1548T
SSA
VSSA 1 VSSO 28 VDDO 2 VCOM 23 VDDA 24
MGC668
VSSA
Fig.1 Block diagram.
1995 Nov 15
4
Philips Semiconductors
Product specification
Bitstream continuous calibration filter-DAC with headphone driver and DSP
PINNING SYMBOL VSSO VCOM VOL FILTCL PIN 1 2 3 4 DESCRIPTION operational amplifier ground common output pin left channel audio voltage output capacitor for left channel first-order filter function should be connected between this pin and VOL (pin 3) mode 0 selection pin mode 1 selection pin bit clock input word select input data input digital supply voltage digital ground system clock 64fs, 256fs or 384fs input format selection 1 input format selection 2 de-emphasis input (fs = 44.1 kHz) (active HIGH) soft-mute input (active HIGH) system clock selection input reference voltage output to external potentiometer analog sense input for treble setting analog sense input for bass boost setting analog sense input for volume control setting 3-position switch input for flat/min/max setting analog supply voltage analog ground internal reference voltage (0.5VDDA typ) capacitor for right channel first-order filter function should be connected between this pin and VOR (pin 27) right channel audio voltage output operational amplifier supply voltage
handbook, halfpage
TDA1548T
MODE0 MODE1 BCK WS DATA VDDD VSSD SYSCLK IF1 IF2 DEEM MUTE CLSEL ADref ADTR ADBB ADVC AD3S VDDA VSSA Vref FILTCR
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
VSSO VCOM VOL FILTCL MODE0
1 2 3 4 5
28 V DDO 27 VOR 26 FILTCR 25 V ref 24 V SSA 23 V DDA 22 AD3S
MODE1 6 BCK WS DATA 7
TDA1548T
8 9 21 ADVC 20 ADBB 19 ADTR 18 AD ref 17 CLSEL 16 MUTE 15 DEEM
MGC669
VDDD 10 VSSD 11 SYSCLK 12 IF1 13 IF2 14
VOR VDDO
27 28
Fig.2 Pin configuration.
1995 Nov 15
5
Philips Semiconductors
Product specification
Bitstream continuous calibration filter-DAC with headphone driver and DSP
FUNCTIONAL DESCRIPTION The TDA1548T CMOS DAC incorporates an up-sampling digital filter, a linear interpolator, a noise shaper, continuous calibrated current sources and headphone amplifiers. The 1fs input data is increased to an oversampling rate of 64fs. This high-rate oversampling, together with the 5-bit DAC, enables the filtering required for waveform smoothing and out-of-band noise reduction to be achieved by simple first-order analog post-filtering. System clock and data input format The TDA1548T accommodates slave mode only, this means that in all applications the system devices must provide the system clock. The system frequency is selectable at pins CLSEL, MODE0 and MODE1 (see Table 1). The TDA1548T supports the following data input modes (see Table 2): I2S-bus with data word length of up to 20 bits LSB justified serial format with data word length of 16, 18 or 20 bits. The input formats are illustrated in Fig.4. Left and right data-channel words are time multiplexed. Analog control of digital sound processing features Digital sound processing settings are controlled via analog sense inputs that translate an analog voltage from, for example, a potentiometer wiper to a digital code, which is then further translated internally to a set of coefficients for either treble, bass boost or volume. The analog input value is acquired by an internal 6-bit ADC, sampling the three input pins ADVC, ADBB and ADTR and the three-mode selection pin ADS3 (see Section "Single pin three mode selection") in a multiplexed fashion. Sampling of the input voltage is performed by a straight forward technique of linear approximation; from the starting value of 0 V, an internal linear approximation voltage is incremented periodically in steps of 1/66th of the scale, with an internal comparator detecting when the approximation value oversteps the input value. Tolerance is built in at the top and bottom end of the scale by dimensioning the resistive elements at the top and bottom of the ladder equals 1R. Thus the ladder is built up of 64 elements of value R, two of value R, making a typical quantization step size of approximately 1.5 V (ADref) divided-by-66 (amount of Rs), equals 22.7 mV.
TDA1548T
For each multiplexed timeslot the full approximation cycle is completed, immediately after which the next input will start being sampled. The time slot for one input lasts 64 steps at a step advance rate of 8 x fs, which amounts to 181 s at fs = 44.1 kHz. Because four inputs are multiplexed, the sample rate for each analog input is 1.38 kHz. A buffered version of an internally generated reference voltage is available at output pin ADref. Because the internal AD derives from the same reference voltage, this allows for optimum mapping of the external analog control value onto the useful AD input voltage range. The idea is to bias a potentiometer to ADref, using a wiper to control the input voltage between 0 V and ADref. Hysteresis is implemented to improve noise immunity of the AD in order to prevent a stable setting of the potentiometer, to a point near a quantization threshold, from producing two alternating digital codes which could give rise to audible volume or boost changes. An hysteresis of 1 LSB is implemented digital. A shift in code must be at least 2 LSB either up or down from the current value, otherwise the internal digital code will remain at the current value. SINGLE PIN THREE MODE SELECTION A special input pin AD3S (pin 22), controls the mode in which the sound processing block operates. Not between two but three modes; whether the DSP should follow the AD inputs applying maximum effect, the minimum effect or overrule the boost effects thereby resulting in a flat frequency characteristic in the treble and bass boost sections. Internally the same AD is used to detect the input level present at this pin as is used for the three sound control pins. An internal bias circuit containing of two MOSTs supplies a mid-range voltage so that this input can be operated with a minimum of external components. A HIGH or LOW input level is created by tying the pin to ADref or ground respectively, the intermediate value is achieved by leaving the pin open-circuit. Volume control Since there is no headroom included into the sound control section, the volume control precedes the sound control. Full volume and neutral setting (flat) of the sound control results in a full-scale output. Any tone boost will immediately cause clipping, which can be avoided by reducing the volume setting.
1995 Nov 15
6
Philips Semiconductors
Product specification
Bitstream continuous calibration filter-DAC with headphone driver and DSP
Soft mute Soft mute is controlled by MUTE (pin 16). When the input is active HIGH the value of the sample is decreased smoothly to zero following a raised cosine curve. 32 coefficients are used to step down the value of the data, each one being used 32 times before stepping on to the next. This amounts to a mute transition time of 23 ms at fs = 44.1 kHz. When MUTE is released (LOW), the samples are returned to the full level again following a raised cosine curve with the same coefficients being used in the reverse order. Mute is synchronized to the sample clock, so that the operation always takes place on complete samples. Digital sound processing features BASS BOOST A strong bass boost effect, which is useful in compensating for poor bass response of portable headphone sets, is implemented digitally in the TDA1548T and can be controlled by ADBB (pin 20) and AD3S (pin 22). Table 3 shows the bass boost values at different input voltages. Table 4 shows the selection mode status (flat/min/max) at different input voltages. Valid settings range from "flat" (no influence on audio) to +18 dB with step sizes of 2 dB in "minimum" and to +24 dB with step sizes of 2 dB in "maximum". The programmable bass boost filter is a second-order shelving type with a fixed corner frequency of 130 Hz for the "minimum" setting and a fixed corner frequency of 230 Hz for the "maximum" setting and has a Butterworth characteristic. Because of the exceptional amount of programmable gain, bass boost should be used in conjunction with adequate prior attenuation, using the volume control. TREBLE A treble effect is implemented digitally in the TDA1548T and can be controlled by ADTR (pin 19) and AD3S (pin 22). Table 3 shows the treble values at different input voltages. Table 4 shows the selection mode status (flat/min/max) at different input voltages. Valid settings range from "flat" (no influence on audio) to +6 dB with step sizes of 2 dB in "minimum" and to +6 dB with a step size of 2 dB in "maximum". The programmable treble filter is a first-order shelving type with a fixed corner frequency of 2.8 kHz for the "minimum" setting and a fixed corner frequency of 5.0 kHz for the "maximum" setting. DE-EMPHASIS De-emphasis is controlled by DEEM (pin 15). The digital de-emphasis filter is dimensioned to produce the 1995 Nov 15 7
TDA1548T
de-emphasis frequency characteristics for the sample rate 44.1 kHz. With its 18-bit dynamic range, the digital de-emphasis of the TDA1548T is a convenient and component-saving alternative to analog de-emphasis. When the DEEM pin is active HIGH, de-emphasis is enabled. De-emphasis is synchronized to the sample clock, so that operation always takes place on complete samples. Oversampling filter and noise shaper The digital filter is a four times oversampling filter. It consists of two sections which each increase the sample rate by 2. The second order noise shaper operates at 64fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique, used in combination with a sign-magnitude coding, enables high signal-to-noise ratios to be achieved. The noise shaper outputs a 5-bit PDM bitstream signal to the DAC. Continuous calibration DAC The dual 5-bit DAC uses the continuous calibration technique. This method, based on charge storage, involves exact duplication of a single reference current source. In the TDA1548T, 32 such current sources plus 1 spare source are continuously calibrated. The spare source is included to allow continuous converter operation. The DAC receives a 5-bit data bitstream from the noise shaper. This data is converted to a sign-magnitude code so that no current is switched to the output during digital silence (input 00000H). In this way very high signal-to-noise performance is achieved. Component-saving stereo headphone driver High precision, low-noise amplifiers together with the internal conversion resistors RCONV1 and RCONV2 convert the converter output current to a voltage capable of driving a line output or headphone. The voltage is available at VOL and VOR (0.64 V RMS typical). A major component saving feature of the TDA1548T is that no DC-blocking capacitors are needed in the application, despite the asymmetrical supply. The VCOM output, pin 2, is biased to the same voltage that the right and left channel voltage outputs are, Vref, and is capable of sinking the sum of left and right channel load currents. Therefore, connecting a load between one of the outputs and VCOM only gives rise to a negligible amount of DC current through the load.
Philips Semiconductors
Product specification
Bitstream continuous calibration filter-DAC with headphone driver and DSP
Table 1 System clock selection PINS DESCRIPTION CLSEL 0 0 0 1 1 1 Table 3 MODE0 0 0 1 0 0 1 MODE1 0 1 X 0 1 X 256fs 64fs reserved 1 384fs reserved 2 reserved 3 IF1 0 0 1 1 IF2 0 1 0 1 Table 2 Data input formats PINS
TDA1548T
FORMAT I2S-bus LSB justified, 16 bits LSB justified, 18 bits LSB justified, 20 bits
Relationship between VC, BB and TR ANALOG INPUT VALUES (V); PINS ADTR, ADBB AND ADVC ADref x 65/66 ADref x 64/66 ADref x 63/66 ADref x 62/66 ADref x 61/66 ADref x 60/66 ADref x 59/66 ADref x 58/66 ADref x 57/66 ADref x 56/66 ADref x 55/66 ADref x 54/66 ADref x 53/66 ADref x 52/66 ADref x 51/66 ADref x 50/66 ADref x 49/66 ADref x 48/66 ADref x 47/66 ADref x 46/66 ADref x 45/66 ADref x 44/66 ADref x /4366 ADref x 42/66 ADref x 41/66 ADref x 40/66 ADref x 39/66 VOLUME (ADVC) -0 -0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 8 BASS BOOST (ADBB) MAX. 0 0 0 0 2 2 4 4 6 6 8 8 10 10 12 12 14 14 16 16 18 18 20 20 22 22 24 MIN. 0 0 0 0 2 2 4 4 6 6 8 8 10 10 12 12 14 14 16 16 18 18 18 18 .... .... .... TREBLE (ADTR) MAX. 0 0 0 0 2 2 2 2 4 4 4 4 6 6 6 6 .... .... .... .... .... .... .... .... .... .... .... MIN. 0 0 0 2 2 2 2 2 4 4 4 4 6 6 6 6 .... .... .... .... .... .... .... .... .... .... ....
1995 Nov 15
Philips Semiconductors
Product specification
Bitstream continuous calibration filter-DAC with headphone driver and DSP
BASS BOOST (ADBB) MAX. ADref x 38/66 ADref x 37/66 ADref x 36/66 .... .... ADref x 5/66 ADref x 4/66 ADref x 3/66 ADref x 2/66 Table 4 Relationship mode selection ANALOG INPUT VALUE (V); PIN AD3S ADref x 65/66 ADref x 64/66 .... .... ADref x 51/66 ADref x 50/66 ADref x 49/66 ADref x 48/66 .... .... ADref x 19/66 ADref x 18/66 ADref x 17/66 ADref x 16/66 .... .... ADref x 3/66 ADref x 2/66 -26 -27 -28 .... .... -59 -60 - - 24 .... .... .... .... 24 24 24 24 MIN. .... .... .... .... .... 18 18 18 18
TDA1548T
ANALOG INPUT VALUES (V); PINS ADTR, ADBB AND ADVC
VOLUME (ADVC)
TREBLE (ADTR) MAX. .... .... .... .... .... 6 6 6 6 MIN. .... .... .... .... .... 6 6 6 6
FLAT, MINIMUM OR MAXIMUM flat flat .... .... flat flat minimum minimum .... .... minimum minimum maximum maximum .... .... maximum maximum
1995 Nov 15
9
Philips Semiconductors
Product specification
Bitstream continuous calibration filter-DAC with headphone driver and DSP
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD Txtal Tstg Tamb Ves PARAMETER supply voltage maximum crystal temperature storage temperature operating ambient temperature electrostatic handling note 2 note 3 Notes 1. All VDD and VSS connections must be made to the same power supply. CONDITIONS note 1 - - -65 -20 -3000 -300 MIN.
TDA1548T
MAX. 4.5 +150 +125 +70 +3000 +300 V
UNIT C C C V V
2. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor. Pin 18 = -1500 V (min) and +1500 V (max). 3. Equivalent to discharging a 200 pF capacitor via a 2.5 H series inductor. THERMAL CHARACTERISTICS SYMBOL Rth j-a SO28 SSOP28 QUALITY SPECIFICATION In accordance with UZW-BO/FQ-0601. The numbers of the quality specification can be found in the "Quality Reference Handbook". The Handbook can be ordered using the code 9397 750 00192. DESCRIPTION thermal resistance from junction to ambient in free air 60 80 K/W K/W VALUE UNIT
1995 Nov 15
10
Philips Semiconductors
Product specification
Bitstream continuous calibration filter-DAC with headphone driver and DSP
TDA1548T
DC CHARACTERISTICS All voltages referenced to ground (pins 1, 11 and 24); VDDD = VDDA = VDDO = 3 V; Tamb = 25 C, RL = 32 (note 1); common operational amplifier application; unless otherwise specified. SYMBOL VDDD VDDA VDDO IDDD IDDA IDDO Ptot VIH VIL |ILI| CI PARAMETER digital supply voltage pin 10 note 2 analog supply voltage pin 23 note 2 opamp supply voltage pin 28 note 2 digital supply current analog supply current opamp supply current total power dissipation at digital silence at digital silence at digital silence; note 3 note 3 CONDITIONS MIN. 2.7 2.7 2.7 - - - - TYP. 3.0 3.0 3.0 4.5 4.5 6.0 50 - - - - MAX. 4.0 4.0 4.0 - - - - - 0.3VDDD 10 10 UNIT V V V mA mA mA mW
Digital inputs HIGH level input voltage on pins 5 to 9 and 12 to 17 LOW level input voltage on pins 5 to 9 and 12 to 17 input leakage current on pins 7 to 9 and 12 to 17 input capacitance on pins 5 to 9 and 12 to 17 0.7VDDD - - - V V A pF
Analog inputs pins ADVC, ADBB, ADTR and AD3S RES CI RI input resolution input capacitance input resistance pins ADBB, ADTR and ADVC pin AD3S Analog reference pin ADref VADref RL(ADref) Vref RO RCONV IO(max) CL Notes 1. RL is the AC impedance of the external circuitry connected to the audio outputs of the application circuit. 2. All power supply pins (VDD and VSS) must be connected to the same external power supply unit. 3. No operational amplifier load resistor. 4. Load capacitance greater than 50 pF, an inductor of 22 H connected in parallel with a resistor of 270 must be inserted between the load and the operational amplifier output. reference voltage pin 18 reference output load pin 18 0.45VDDA 3.0 0.5VDDA - 0.55VDDA - V k - - 1 - - 10 - 20 6 - - - bit pF M k
Analog audio pins reference voltage pin 25 output resistance pin 25 current-to-voltage conversion resistor maximum output current output load capacitance (THD + N)/S < 0.1% note 4 with respect to VSSO 0.45VDDA - - - - 0.5VDDA 3 1.2 35 - 0.55VDDA - - - 50 V k k mA pF
1995 Nov 15
11
Philips Semiconductors
Product specification
Bitstream continuous calibration filter-DAC with headphone driver and DSP
TDA1548T
AC CHARACTERISTICS (ANALOG) All voltages referenced to ground (pins 2, 9 and 23); VDDD = VDDA = VDDO = 3 V; fi = 1 kHz; Tamb = 25 C, RL = 32 (note 1); common operational amplifier application; unless otherwise specified. SYMBOL RES fsAD VADref VFS(rms) VDC(os) PARAMETER input resolution AD sample frequency input voltage range output voltage swing (RMS value) (pins 3 and 27) DC offset output voltage w.r.t. reference voltage level Vref full scale temperature coefficient supply voltage ripple rejection VDDA and VDDO unbalance between the 2 DAC voltage outputs (pins 3 and 27) crosstalk between the 2 DAC voltage outputs (pins 3 and 27) C25 = 10 F; fripple = 1 kHz; Vripple = 100 mV (peak) maximum volume CONDITIONS - - 0 0.57 - MIN. - fs/32 - 0.64 20 TYP. - VADref 0.71 - MAX. 18 UNIT bit kHz V V mV
TCFS SVRR UNBAL
- - -
100 x 10-6 40 0.1
- - - dB dB
ct
one output digital silence the - other maximum volume one output digital silence the - other maximum volume RL = 5 k one output digital silence the - other maximum volume one output digital silence the - other maximum volume RL = 5 k 0 dB signal 0 dB signal; RL = 5 k -60 dB signal; RL = 32 or RL = 5 k - - - - - - 90
50 90
- -
dB dB
crosstalk between the 2 DAC voltage outputs (pins 3 and 27) with RL connected to ground (THD+N)/S total harmonic distortion plus noise as a function of signal
70 100
- -
dB dB
-65 0.056 -85 0.006 -35 1.778 95
-60 0.1 -78 0.013 -30 3.162 -
dB % dB % dBA % dBA
S/N Note
signal-to-noise ratio at bipolar zero
A-weighted at code 00000H
1. RL is the AC impedance of the external circuitry connected to the audio outputs of the application circuit.
1995 Nov 15
12
Philips Semiconductors
Product specification
Bitstream continuous calibration filter-DAC with headphone driver and DSP
TDA1548T
AC CHARACTERISTICS (DIGITAL) All voltages referenced to ground (pins 2, 9 and 23); VDDD = VDDA = VDDO = 2.7 to 4.0 V; Tamb = +70 C, RL = 32 (note 1); unless otherwise specified. SYMBOL Tcy PARAMETER clock cycle CONDITIONS fsys = 384fs fsys = 256fs fsys = 64fs tCW(L) tCW(H) BR fsys LOW level pulse width fsys HIGH level pulse width clock input = data input rate fsys = 384fs fsys = 256fs fsys = 64fs fsys fWS tr tf tBCK(H) tBCK(L) ts;DAT th;DAT ts;WS th;WS system clock frequency word select input frequency rise time fall time bit clock HIGH time bit clock LOW time data set-up time data hold time word select set-up time word select hold time MIN. 54.2 81.3 325.5 22 22 - - - 2.048 - - - 55 55 20 10 20 10 TYP. 59.1 88.6 354.3 - - MAX. 81.3 122 488.3 - - - - - 18.432 48.0 20 20 - - - - - - MHz kHz ns ns ns ns ns ns ns ns UNIT ns ns ns ns ns
Serial input data timing (see Fig.3) 48fs 64fs 64fs - 44.1 - - - - - - - -
LEFT
handbook, full pagewidth
WS tBCK(H)
RIGHT th;WS t BCK(L)
ts;WS
BCK tr tr Tcy ts;DAT
t
h;DAT
DATA
LSB
MSB
MGC670
SAMPLE OUT
Fig.3 Timing of input signals.
1995 Nov 15
13
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WS LEFT BCK 1 DATA MSB B2 MSB B2 INPUT FORMAT I2 S WS LEFT 16 BCK DATA MSB B2 B15 LSB LSB JUSTIFIED FORMAT 16 BITS MSB B2 B15 LSB 15 2 1 RIGHT 16 15 2 1 MSB 2 3 >=8 1 2 3 RIGHT >=8
Philips Semiconductors
Bitstream continuous calibration filter-DAC with headphone driver and DSP
Fig.4 Data input formats.
handbook, full pagewidth
14
WS BCK DATA MSB B2 B3 B4 B17 LSB LSB JUSTIFIED FORMAT 18 BITS WS BCK DATA MSB B2 B3 B4 B5 B6 B19 LSB LSB JUSTIFIED FORMAT 20 BITS MSB B2 B3 B4 B5 B6 B19 LSB
MGC671
LEFT 18
RIGHT 17 16 15 2 1 18 17 16 15 2 1
MSB
B2
B3
B4
B17 LSB
20
19
LEFT 18
RIGHT 17 16 15 2 1 20 19 18 17 16 15 2 1
Product specification
TDA1548T
Philips Semiconductors
Product specification
Bitstream continuous calibration filter-DAC with headphone driver and DSP
TEST AND APPLICATION INFORMATION Filter characteristics Table 5 Digital filter characteristics (fs = 44.1 kHz) The band frequencies scale with the sample frequency. BAND 0 to 20 kHz 24 to 64 kHz 64 to 69 kHz 69 to 88 kHz ATTENUATION < 0.001 dB > 39 dB > 33 dB > 37 dB
TDA1548T
handbook, full pagewidth
+3 V 100 F 100 nF
(1)
100 F 100 nF L3 (2) 100 nF
VSSD VDDD VSSA VDDA VSSO VDDO 11 SYSTEM CLOCK INPUT I S-BUS OR LSB-JUSTIFIED SERIAL INPUT DATA
2
10
24
23
1
28 25 Vref 100 nF 4.7 F 100 26 FILTCR 1 nF R2(1) 330 L2(1) 22 H VCOM VOL 1 nF 4 FILTCL L1(1) 22 H R1(1) 330 100 47 F LEFT 47 F RIGHT
SYSCLK
12
BCK WS DATA
7 8 9
MODE0 MODE1 IF1 IF2 DEEM MUTE +3 V FLAT MID MAX CLSEL
5 6 13 14 15 16 17
27
VOR
TDA1548T
2 3
10 k
AD3S
22 18 ADref 19 ADTR 1 k 20 ADBB 1 k 21 ADVC 1 k
C(1)
C(1)
C(1)
2 k 6 k
5 k 5 k
10 k
MGB709
(1) Optional. (2) Chip inductor BLM32A07.
Fig.5 Application diagram.
1995 Nov 15
15
Philips Semiconductors
Product specification
Bitstream continuous calibration filter-DAC with headphone driver and DSP
PACKAGE OUTLINES SO28: plastic small outline package; 28 leads; body width 7.5 mm
TDA1548T
SOT136-1
D
E
A X
c y HE vMA
Z 28 15
Q A2 A1 pin 1 index Lp L 1 e bp 14 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 18.1 17.7 0.71 0.69 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
8o 0o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT136-1 REFERENCES IEC 075E06 JEDEC MS-013AE EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-24 97-05-22
1995 Nov 15
16
Philips Semiconductors
Product specification
Bitstream continuous calibration filter-DAC with headphone driver and DSP
TDA1548T
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
SOT341-1
D
E
A X
c y HE vMA
Z 28 15
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 14 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.0 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 10.4 10.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.1 0.7 8 0o
o
Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 REFERENCES IEC JEDEC MO-150AH EIAJ EUROPEAN PROJECTION
ISSUE DATE 93-09-08 95-02-04
1995 Nov 15
17
Philips Semiconductors
Product specification
Bitstream continuous calibration filter-DAC with headphone driver and DSP
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all SO and SSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering SO Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. SSOP
TDA1548T
Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). METHOD (SO AND SSOP) During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1995 Nov 15
18
Philips Semiconductors
Product specification
Bitstream continuous calibration filter-DAC with headphone driver and DSP
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA1548T
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1995 Nov 15
19
Philips Semiconductors - a worldwide company
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Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-2724825 SCD45 (c) Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands


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